Diseño de sumador completo rápido de baja potencia utilizando Domino Logic basado en Unión de Túnel Magnético (UTM) y Memristor
DOI:
https://doi.org/10.54139/revinguc.v27i3.148Palabras clave:
MTJ, Memristor, Domino Logic, Sumador completoResumen
Los circuitos CMOS de Domino se utilizan ampliamente en sistemas integrados de gran escala (VLSI) de alto rendimiento. La topología de los circuitos dominó para operación de alta velocidad, menor consumo de energía y robustez es de gran importancia en el diseño de sistemas digitales. El presente artículo propone un circuito sumador completo de baja potencia y alta velocidad, que utiliza una nueva familia lógica de dominó CMOS basada en elementos de unión de túnel magnético (UTM) y memristor en la técnica de entrada de difusión de puerta (GDI). En comparación con un circuito lógico CMOS estático, un circuito lógico dinámico es importante ya que proporciona una mayor velocidad y requiere menos transistores. En comparación con los circuitos propuestos recientemente para estilos lógicos dinámicos, las características del circuito propuesto son un consumo de energía dinámica muy bajo y menos retardo. El problema con los circuitos dinámicos es la falta de una salida estable en diferentes momentos, mientras que el circuito propuesto conserva el valor de salida utilizando elementos de memoria como UTM y memristor durante el ciclo de reloj. La técnica propuesta muestra un consumo máximo de energía de 0,317 µW en sumadores completos basados en MTJ/Memristor. Además, la técnica propuesta muestra un retraso máximo de 0,35 ns. Se simula el sumador completo propuesto, y su disipación de potencia y rendimiento se analizan utilizando HSPICE en tecnología CMOS estándar de 7 nm.
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Esta obra está bajo una licencia internacional Creative Commons Atribución-NoComercial-SinDerivadas 4.0.
