Design of low power fast full adder using Domino Logic based on magnetic tunnel junction (MTJ) and memristor
DOI:
https://doi.org/10.54139/revinguc.v27i3.148Keywords:
MTJ, Memristor, Domino Logic, Full AdderAbstract
Domino CMOS circuits are widely used in high-performance very large scale integrated (VLSI) systems. The topology of domino circuits for high-speed operation, lower power consumption and robustness is of great importance in designing digital systems. The present paper proposes a low-power high-speed full adder circuit, which uses a new CMOS domino logic family based on magnetic tunnel junction (MTJ) elements and memristor in gate diffusion input (GDI) technique. In comparison with a static CMOS logic circuit, a dynamic logic circuit is of importance since it provides higher speed and requires fewer transistors. In comparison with the recently proposed circuits for dynamic logic styles, very low dynamic power consumption and less delay are the features of the proposed circuit. The problem with dynamic circuits is the lack of a stable output at different times, while the proposed circuit preserves the output value using memory elements such as MTJ and memristor during the clock cycle. The proposed technique shows a maximum power consumption of 0,317 µW in MTJ/memristor-based full adders. Moreover, the proposed technique shows a maximum delay of 0,35 ns. The proposed full adder is simulated, and its power dissipation and performance are analyzed using HSPICE in standard 7 nm CMOS technology.
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